Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

Xiaofang Wang; Sotirios G. Ziavras

doi:10.1109/FPT.2003.1275763

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

Xiaofang Wang, Sotirios G. Ziavras

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

Several driving forces have recently brought about significant advances in the field of configurable computing. They have also enabled parallel processing within a single field-programmable gate array (FPGA) chip. The ever-increasing complexity of application algorithms and the supercomputing crisis have made this new parallel-processing approach more important and pertinent. Its cost-effectiveness provides system designers with the greatest flexibility while imposing many challenges to current hardware and software codesign methodologies. This paper explores practical hardware and software design and implementation issues for FPGA-based configurable multiprocessors, based on the authors' first-hand experience with a shared-memory implementation of parallel LU factorization for sparse block-diagonal-bordered (BDB) matrices. We also propose a new dynamic load balancing strategy for parallel LU factorization on our system. Performance results are included to prove the viability of this new multiprocessor design approach.

Original language	English (US)
Title of host publication	Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	303-306
Number of pages	4
ISBN (Electronic)	0780383206, 9780780383203
DOIs	https://doi.org/10.1109/FPT.2003.1275763
State	Published - 2003
Event	2nd International Conference on Field Programmable Technology, FPT 2003 - Tokyo, Japan Duration: Dec 15 2003 → Dec 17 2003

Publication series

Name	Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003

Other

Other	2nd International Conference on Field Programmable Technology, FPT 2003
Country/Territory	Japan
City	Tokyo
Period	12/15/03 → 12/17/03

All Science Journal Classification (ASJC) codes

Computer Science Applications
Software

Access to Document

10.1109/FPT.2003.1275763

Cite this

Wang, X., & Ziavras, S. G. (2003). Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. In Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003 (pp. 303-306). Article 1275763 (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPT.2003.1275763

Wang, Xiaofang ; Ziavras, Sotirios G. / Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 303-306 (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003).

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abstract = "Several driving forces have recently brought about significant advances in the field of configurable computing. They have also enabled parallel processing within a single field-programmable gate array (FPGA) chip. The ever-increasing complexity of application algorithms and the supercomputing crisis have made this new parallel-processing approach more important and pertinent. Its cost-effectiveness provides system designers with the greatest flexibility while imposing many challenges to current hardware and software codesign methodologies. This paper explores practical hardware and software design and implementation issues for FPGA-based configurable multiprocessors, based on the authors' first-hand experience with a shared-memory implementation of parallel LU factorization for sparse block-diagonal-bordered (BDB) matrices. We also propose a new dynamic load balancing strategy for parallel LU factorization on our system. Performance results are included to prove the viability of this new multiprocessor design approach.",

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year = "2003",

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language = "English (US)",

series = "Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003",

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Wang, X & Ziavras, SG 2003, Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. in Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003., 1275763, Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003, Institute of Electrical and Electronics Engineers Inc., pp. 303-306, 2nd International Conference on Field Programmable Technology, FPT 2003, Tokyo, Japan, 12/15/03. https://doi.org/10.1109/FPT.2003.1275763

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. / Wang, Xiaofang; Ziavras, Sotirios G.
Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 303-306 1275763 (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Wang X, Ziavras SG. Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. In Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 303-306. 1275763. (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003). doi: 10.1109/FPT.2003.1275763

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

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