Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

Keyphrases

• Array chip 33%
• Array-based 100%
• Block Diagonal 33%
• Bordered Matrix 33%
• Co-design Method 33%
• Configurable Computing 33%
• Cost-effectiveness 33%
• Design Approach 33%
• Dynamic Load Balancing 33%
• Field Programmable Gate Arrays 100%
• First-year Experience 33%
• Hardware Design 33%
• Increasing Complexity 33%
• Load Balancing Algorithm 33%
• Matrix Operation 100%
• Multiprocessor 100%
• One Field 33%
• Parallel LU Factorization 66%
• Parallel Processing 66%
• Performance Optimization 100%
• Performance Results 33%
• Shared Memory 33%
• Software Design 33%
• Software Implementation 33%
• System Designer 33%

Computer Science

• Block Diagonal 33%
• Dynamic Load Balancing 33%
• Field Programmable Gate Arrays 100%
• Implementation Issue 33%
• Matrix Operation 100%
• multi-processor 100%
• Multiprocessor Design 33%
• Parallel Processing 66%
• Performance Optimization 100%
• Processing Approach 33%
• Shared Memories 33%
• Software Codesign 33%
• Software Design 33%
• System Designer 33%