Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

I. Sajid, M. M. Ahmed, Sotirios Ziavras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible and can be modified as per the need of an application. The performance of the proposed system, as a function of execution time and power consumption per operation, has been compared with other floating point pipelined implementations. It is demonstrated that the proposed system is ∼ 2 times efficient compared to its counterparts.

Original languageEnglish (US)
Title of host publication2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Pages226-230
Number of pages5
DOIs
StatePublished - May 28 2010
Event2nd International Conference on Computer and Automation Engineering, ICCAE 2010 - Singapore, Singapore
Duration: Feb 26 2010Feb 28 2010

Publication series

Name2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Volume3

Other

Other2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Country/TerritorySingapore
CitySingapore
Period2/26/102/28/10

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Computer Science Applications
  • Control and Systems Engineering

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