Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

I. Sajid; M. M. Ahmed; Sotirios Ziavras

doi:10.1109/ICCAE.2010.5452039

Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

I. Sajid, M. M. Ahmed, Sotirios Ziavras

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible and can be modified as per the need of an application. The performance of the proposed system, as a function of execution time and power consumption per operation, has been compared with other floating point pipelined implementations. It is demonstrated that the proposed system is ∼ 2 times efficient compared to its counterparts.

Original language	English (US)
Title of host publication	2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Pages	226-230
Number of pages	5
DOIs	https://doi.org/10.1109/ICCAE.2010.5452039
State	Published - May 28 2010
Event	2nd International Conference on Computer and Automation Engineering, ICCAE 2010 - Singapore, Singapore Duration: Feb 26 2010 → Feb 28 2010

Publication series

Name	2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Volume	3

Other

Other	2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Country/Territory	Singapore
City	Singapore
Period	2/26/10 → 2/28/10

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Computer Science Applications
Control and Systems Engineering

Access to Document

10.1109/ICCAE.2010.5452039

Cite this

Sajid, I., Ahmed, M. M., & Ziavras, S. (2010). Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm. In 2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010 (pp. 226-230). Article 5452039 (2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010; Vol. 3). https://doi.org/10.1109/ICCAE.2010.5452039

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title = "Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm",

abstract = "Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible and can be modified as per the need of an application. The performance of the proposed system, as a function of execution time and power consumption per operation, has been compared with other floating point pipelined implementations. It is demonstrated that the proposed system is ∼ 2 times efficient compared to its counterparts.",

author = "I. Sajid and Ahmed, {M. M.} and Sotirios Ziavras",

year = "2010",

month = may,

day = "28",

doi = "10.1109/ICCAE.2010.5452039",

language = "English (US)",

isbn = "9781424455850",

series = "2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010",

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booktitle = "2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010",

note = "2nd International Conference on Computer and Automation Engineering, ICCAE 2010 ; Conference date: 26-02-2010 Through 28-02-2010",

}

Sajid, I, Ahmed, MM & Ziavras, S 2010, Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm. in 2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010., 5452039, 2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010, vol. 3, pp. 226-230, 2nd International Conference on Computer and Automation Engineering, ICCAE 2010, Singapore, Singapore, 2/26/10. https://doi.org/10.1109/ICCAE.2010.5452039

Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm. / Sajid, I.; Ahmed, M. M.; Ziavras, Sotirios.
2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010. 2010. p. 226-230 5452039 (2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible and can be modified as per the need of an application. The performance of the proposed system, as a function of execution time and power consumption per operation, has been compared with other floating point pipelined implementations. It is demonstrated that the proposed system is ∼ 2 times efficient compared to its counterparts.

AB - Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible and can be modified as per the need of an application. The performance of the proposed system, as a function of execution time and power consumption per operation, has been compared with other floating point pipelined implementations. It is demonstrated that the proposed system is ∼ 2 times efficient compared to its counterparts.

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Sajid I, Ahmed MM, Ziavras S. Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm. In 2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010. 2010. p. 226-230. 5452039. (2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010). doi: 10.1109/ICCAE.2010.5452039

Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

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