Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

Computer Science

• Fixed Points 100%
• Pipelined Implementation 100%
• Power Consumption 50%
• Arithmetic Operation 50%
• Execution Time 50%
• Floating Point 50%
• Pipelining 50%
• Time Consumption 50%
• pipelined architecture 50%
• Signal Processing Algorithm 50%
• Image Processing Algorithm 50%

Keyphrases

• Pipeline Implementation 100%
• Square Root 100%
• Non-restoring Algorithm 100%
• Power Consumption 33%
• Signal Processing Algorithms 33%
• Proposed Architecture 33%
• Time Consumption 33%
• Arithmetic Operations 33%
• Execution Time 33%
• Pipelined Architecture 33%
• Floating-point 33%
• Imaging Algorithm 33%
• Latency Time 33%