Power-constrained DFT algorithms for non-scan BIST-able RTL data paths

Zhiqiang You, Ken'ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara

Research output: Contribution to journalConference articlepeer-review


This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our new approaches.

Original languageEnglish (US)
Pages (from-to)32-39
Number of pages8
JournalProceedings of the Asian Test Symposium
StatePublished - 2004
EventProceedings of the Asian Test Symposium, ATS'04 - Kenting, Taiwan, Province of China
Duration: Nov 15 2004Nov 17 2004

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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