Abstract
This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our new approaches.
Original language | English (US) |
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Pages (from-to) | 32-39 |
Number of pages | 8 |
Journal | Proceedings of the Asian Test Symposium |
State | Published - 2004 |
Event | Proceedings of the Asian Test Symposium, ATS'04 - Kenting, Taiwan, Province of China Duration: Nov 15 2004 → Nov 17 2004 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering