This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our new approaches.
|Number of pages
|Proceedings of the Asian Test Symposium
|Published - Dec 1 2004
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering