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Power-constrained DFT algorithms for non-scan BIST-able RTL data paths
Zhiqiang You
, Ken'ichi Yamaguchi
, Michiko Inoue
,
Jacob Savir
, Hideo Fujiwara
Electrical and Computer Engineering
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Keyphrases
DFT Algorithm
100%
Constrained DFT
100%
Power Limit
100%
Energy Dissipation
50%
Design Parameters
50%
Scheduling Algorithm
50%
Synthetic Schemes
50%
Parameter Dependence
50%
Appropriate Design
50%
Hardware Overhead
50%
Test Synthesis
50%
Constrained Test Problems
50%
Good Performance
50%
Testing Rates
50%
Low Hardware Overhead
50%
Computer Science
Density Functional Theory
100%
Hardware Overhead
100%
Design Parameter
50%
Experimental Result
50%
Scheduling Algorithm
50%
Test Application Time
50%
Good Performance
50%
Energy Dissipation
50%