Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths

Zhiqiang You, Ken'ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.

Original languageEnglish (US)
Pages (from-to)1940-1946
Number of pages7
JournalIEICE Transactions on Information and Systems
VolumeE88-D
Issue number8
DOIs
StatePublished - Aug 2005

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence
  • Electrical and Electronic Engineering

Keywords

  • Built-in self-test
  • Design for testability
  • Low power testing
  • RTL data path
  • Test scheduling

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