Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths

Zhiqiang You; Ken'ichi Yamaguchi; Michiko Inoue; Jacob Savir; Hideo Fujiwara

doi:10.1093/ietisy/e88-d.8.1940

Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths

Zhiqiang You, Ken'ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.

Original language	English (US)
Pages (from-to)	1940-1946
Number of pages	7
Journal	IEICE Transactions on Information and Systems
Volume	E88-D
Issue number	8
DOIs	https://doi.org/10.1093/ietisy/e88-d.8.1940
State	Published - Aug 2005

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Computer Vision and Pattern Recognition
Electrical and Electronic Engineering
Artificial Intelligence

Keywords

Built-in self-test
Design for testability
Low power testing
RTL data path
Test scheduling

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10.1093/ietisy/e88-d.8.1940

Cite this

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abstract = "This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.",

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AU - Savir, Jacob

AU - Fujiwara, Hideo

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AB - This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.

KW - Built-in self-test

KW - Design for testability

KW - Low power testing

KW - RTL data path

KW - Test scheduling

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Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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