Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths

Keyphrases

• Appropriate Design 50%
• Constrained Test Problems 100%
• Design Parameters 50%
• Hardware Overhead 50%
• Low Computational Complexity 50%
• Parameter Dependence 50%
• Power Constrained 100%
• Power Dissipation 50%
• Scheduling Algorithm 100%
• Synthesis Algorithm 100%
• Test Scheduling 100%
• Test Synthesis 100%
• Testing Time 50%

Computer Science

• Design Parameter 50%
• Experimental Result 50%
• Good Performance 50%
• Hardware Overhead 100%
• Power Dissipation 50%
• Scheduling Algorithm 100%
• Synthesis Algorithm 100%
• Test Application Time 50%