Power flow analysis on an FPGA-based vector computer

Muhammad Z. Hasan; Sotirios G. Ziavras; Tae Gyu Chang

Power flow analysis on an FPGA-based vector computer

Muhammad Z. Hasan, Sotirios G. Ziavras, Tae Gyu Chang

Research output: Contribution to journal › Conference article › peer-review

Abstract

The solution to a set of linear equations given in the form Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained with the W-matrix method for power flow studies. The characteristics of this method are explored here for sparse linear systems present in such studies and an enhanced vector processor is proposed to support them directly in hardware. The effects of customized instructions, instruction chaining, and matrix density are evaluated. The impact of multiple pipelined functional units, multiple data buses, and vector register size is analyzed as well. Our implementation of the vector processor on an FPGA (Field-Programmable Gate Array) is discussed and benchmark results are presented.

Original language	English (US)
Article number	492-060
Pages (from-to)	96-99
Number of pages	4
Journal	Series on Energy and Power Systems
State	Published - 2005
Event	5th IASTED International Conference on Power and Energy Systems, PES 2005 - Marina del Rey, CA, United States Duration: Oct 24 2005 → Oct 26 2005

All Science Journal Classification (ASJC) codes

General Engineering

Keywords

FPGA
Power flow
Sparse matrix
Vector computer

Cite this

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title = "Power flow analysis on an FPGA-based vector computer",

abstract = "The solution to a set of linear equations given in the form Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained with the W-matrix method for power flow studies. The characteristics of this method are explored here for sparse linear systems present in such studies and an enhanced vector processor is proposed to support them directly in hardware. The effects of customized instructions, instruction chaining, and matrix density are evaluated. The impact of multiple pipelined functional units, multiple data buses, and vector register size is analyzed as well. Our implementation of the vector processor on an FPGA (Field-Programmable Gate Array) is discussed and benchmark results are presented.",

keywords = "FPGA, Power flow, Sparse matrix, Vector computer",

author = "Hasan, {Muhammad Z.} and Ziavras, {Sotirios G.} and Chang, {Tae Gyu}",

year = "2005",

language = "English (US)",

pages = "96--99",

journal = "Series on Energy and Power Systems",

issn = "1482-7891",

note = "5th IASTED International Conference on Power and Energy Systems, PES 2005 ; Conference date: 24-10-2005 Through 26-10-2005",

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TY - JOUR

T1 - Power flow analysis on an FPGA-based vector computer

AU - Hasan, Muhammad Z.

AU - Ziavras, Sotirios G.

AU - Chang, Tae Gyu

PY - 2005

Y1 - 2005

N2 - The solution to a set of linear equations given in the form Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained with the W-matrix method for power flow studies. The characteristics of this method are explored here for sparse linear systems present in such studies and an enhanced vector processor is proposed to support them directly in hardware. The effects of customized instructions, instruction chaining, and matrix density are evaluated. The impact of multiple pipelined functional units, multiple data buses, and vector register size is analyzed as well. Our implementation of the vector processor on an FPGA (Field-Programmable Gate Array) is discussed and benchmark results are presented.

AB - The solution to a set of linear equations given in the form Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained with the W-matrix method for power flow studies. The characteristics of this method are explored here for sparse linear systems present in such studies and an enhanced vector processor is proposed to support them directly in hardware. The effects of customized instructions, instruction chaining, and matrix density are evaluated. The impact of multiple pipelined functional units, multiple data buses, and vector register size is analyzed as well. Our implementation of the vector processor on an FPGA (Field-Programmable Gate Array) is discussed and benchmark results are presented.

KW - FPGA

KW - Power flow

KW - Sparse matrix

KW - Vector computer

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M3 - Conference article

AN - SCOPUS:30644479063

SN - 1482-7891

SP - 96

EP - 99

JO - Series on Energy and Power Systems

JF - Series on Energy and Power Systems

M1 - 492-060

T2 - 5th IASTED International Conference on Power and Energy Systems, PES 2005

Y2 - 24 October 2005 through 26 October 2005

ER -

Power flow analysis on an FPGA-based vector computer

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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