Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration

Lane-based Vector Processors (VPs) are highly scalable. However, they become less energy efficient as they scale for vector applications having insufficient data-level parallelism (DLP) to keep the extra computation lanes fully occupied. We present a scalable and yet flexible VP that is capable of dynamically deactivating some of its computing lanes in order to reduce static power with minimum performance loss. In addition, our simultaneous multi-threaded (SMT) VP can exploit identical instruction flows that may be present in different vector applications by running in a novel fused mode that increases its utilization. We introduce a power model and two optimization policies for minimizing the consumed energy, or the product of the energy and runtime for a given application. Benchmarking that involves an FPGA prototype shows up to 33.8% energy reduction in addition to 40% runtime improvement, or up to 62.7% reduction in the product of energy and runtime.