Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration

Yaojie Lu; Seyedamin Rooholamin; Sotirios Ziavras

doi:10.1109/ISVLSI.2016.27

Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration

Yaojie Lu, Seyedamin Rooholamin, Sotirios Ziavras

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Lane-based Vector Processors (VPs) are highly scalable. However, they become less energy efficient as they scale for vector applications having insufficient data-level parallelism (DLP) to keep the extra computation lanes fully occupied. We present a scalable and yet flexible VP that is capable of dynamically deactivating some of its computing lanes in order to reduce static power with minimum performance loss. In addition, our simultaneous multi-threaded (SMT) VP can exploit identical instruction flows that may be present in different vector applications by running in a novel fused mode that increases its utilization. We introduce a power model and two optimization policies for minimizing the consumed energy, or the product of the energy and runtime for a given application. Benchmarking that involves an FPGA prototype shows up to 33.8% energy reduction in addition to 40% runtime improvement, or up to 62.7% reduction in the product of energy and runtime.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Publisher	IEEE Computer Society
Pages	81-86
Number of pages	6
Volume	2016-September
ISBN (Electronic)	9781467390385
DOIs	https://doi.org/10.1109/ISVLSI.2016.27
State	Published - Sep 2 2016
Event	15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 - Pittsburgh, United States Duration: Jul 11 2016 → Jul 13 2016

Other

Other	15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Country/Territory	United States
City	Pittsburgh
Period	7/11/16 → 7/13/16

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/ISVLSI.2016.27

Cite this

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title = "Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration",

abstract = "Lane-based Vector Processors (VPs) are highly scalable. However, they become less energy efficient as they scale for vector applications having insufficient data-level parallelism (DLP) to keep the extra computation lanes fully occupied. We present a scalable and yet flexible VP that is capable of dynamically deactivating some of its computing lanes in order to reduce static power with minimum performance loss. In addition, our simultaneous multi-threaded (SMT) VP can exploit identical instruction flows that may be present in different vector applications by running in a novel fused mode that increases its utilization. We introduce a power model and two optimization policies for minimizing the consumed energy, or the product of the energy and runtime for a given application. Benchmarking that involves an FPGA prototype shows up to 33.8% energy reduction in addition to 40% runtime improvement, or up to 62.7% reduction in the product of energy and runtime.",

author = "Yaojie Lu and Seyedamin Rooholamin and Sotirios Ziavras",

year = "2016",

month = sep,

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doi = "10.1109/ISVLSI.2016.27",

language = "English (US)",

volume = "2016-September",

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booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016",

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address = "United States",

note = "15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 ; Conference date: 11-07-2016 Through 13-07-2016",

}

Lu, Y, Rooholamin, S & Ziavras, S 2016, Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration. in Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016. vol. 2016-September, 7560177, IEEE Computer Society, pp. 81-86, 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, United States, 7/11/16. https://doi.org/10.1109/ISVLSI.2016.27

Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration. / Lu, Yaojie; Rooholamin, Seyedamin; Ziavras, Sotirios.

Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016. Vol. 2016-September IEEE Computer Society, 2016. p. 81-86 7560177.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Lane-based Vector Processors (VPs) are highly scalable. However, they become less energy efficient as they scale for vector applications having insufficient data-level parallelism (DLP) to keep the extra computation lanes fully occupied. We present a scalable and yet flexible VP that is capable of dynamically deactivating some of its computing lanes in order to reduce static power with minimum performance loss. In addition, our simultaneous multi-threaded (SMT) VP can exploit identical instruction flows that may be present in different vector applications by running in a novel fused mode that increases its utilization. We introduce a power model and two optimization policies for minimizing the consumed energy, or the product of the energy and runtime for a given application. Benchmarking that involves an FPGA prototype shows up to 33.8% energy reduction in addition to 40% runtime improvement, or up to 62.7% reduction in the product of energy and runtime.

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Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration

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