Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience

Arman Roohi; Shaahin Angizi; Deliang Fan; Ronald F. Demara

doi:10.1109/ISQED.2019.8697572

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience

Arman Roohi, Shaahin Angizi, Deliang Fan, Ronald F. Demara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Scopus citations

Abstract

Herein, a bit-wise Convolutional Neural Network (CNN) in-memory accelerator is implemented using Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) computational sub-arrays. It utilizes a novel AND-Accumulation method capable of significantly-reduced energy consumption within convolutional layers and performs various low bitwidth CNN inference operations entirely within MRAM. Power-intermittence resiliency is also enhanced by retaining the partial state information needed to maintain computational forward-progress, which is advantageous for battery-less IoT nodes. Simulation results indicate ∼ 5.4× higher energy-efficiency and 9× speedup over ReRAM-based acceleration, or roughly ∼ 9.7× higher energy-efficiency and 13.5× speedup over recent CMOS-only approaches, while maintaining inference accuracy comparable to baseline designs.

Original language	English (US)
Title of host publication	Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
Publisher	IEEE Computer Society
Pages	8-13
Number of pages	6
ISBN (Electronic)	9781728103921
DOIs	https://doi.org/10.1109/ISQED.2019.8697572
State	Published - Apr 23 2019
Externally published	Yes
Event	20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States Duration: Mar 6 2019 → Mar 7 2019

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2019-March
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	20th International Symposium on Quality Electronic Design, ISQED 2019
Country/Territory	United States
City	Santa Clara
Period	3/6/19 → 3/7/19

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISQED.2019.8697572

Cite this

Roohi, A., Angizi, S., Fan, D., & Demara, R. F. (2019). Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 (pp. 8-13). Article 8697572 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2019.8697572

Roohi, Arman ; Angizi, Shaahin ; Fan, Deliang et al. / Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience. Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. pp. 8-13 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

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title = "Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience",

abstract = "Herein, a bit-wise Convolutional Neural Network (CNN) in-memory accelerator is implemented using Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) computational sub-arrays. It utilizes a novel AND-Accumulation method capable of significantly-reduced energy consumption within convolutional layers and performs various low bitwidth CNN inference operations entirely within MRAM. Power-intermittence resiliency is also enhanced by retaining the partial state information needed to maintain computational forward-progress, which is advantageous for battery-less IoT nodes. Simulation results indicate ∼ 5.4× higher energy-efficiency and 9× speedup over ReRAM-based acceleration, or roughly ∼ 9.7× higher energy-efficiency and 13.5× speedup over recent CMOS-only approaches, while maintaining inference accuracy comparable to baseline designs.",

author = "Arman Roohi and Shaahin Angizi and Deliang Fan and Demara, {Ronald F.}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 20th International Symposium on Quality Electronic Design, ISQED 2019 ; Conference date: 06-03-2019 Through 07-03-2019",

year = "2019",

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doi = "10.1109/ISQED.2019.8697572",

language = "English (US)",

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Roohi, A, Angizi, S, Fan, D & Demara, RF 2019, Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience. in Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019., 8697572, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2019-March, IEEE Computer Society, pp. 8-13, 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, United States, 3/6/19. https://doi.org/10.1109/ISQED.2019.8697572

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience. / Roohi, Arman; Angizi, Shaahin; Fan, Deliang et al.
Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 8-13 8697572 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Demara, Ronald F.

PY - 2019/4/23

Y1 - 2019/4/23

N2 - Herein, a bit-wise Convolutional Neural Network (CNN) in-memory accelerator is implemented using Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) computational sub-arrays. It utilizes a novel AND-Accumulation method capable of significantly-reduced energy consumption within convolutional layers and performs various low bitwidth CNN inference operations entirely within MRAM. Power-intermittence resiliency is also enhanced by retaining the partial state information needed to maintain computational forward-progress, which is advantageous for battery-less IoT nodes. Simulation results indicate ∼ 5.4× higher energy-efficiency and 9× speedup over ReRAM-based acceleration, or roughly ∼ 9.7× higher energy-efficiency and 13.5× speedup over recent CMOS-only approaches, while maintaining inference accuracy comparable to baseline designs.

AB - Herein, a bit-wise Convolutional Neural Network (CNN) in-memory accelerator is implemented using Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) computational sub-arrays. It utilizes a novel AND-Accumulation method capable of significantly-reduced energy consumption within convolutional layers and performs various low bitwidth CNN inference operations entirely within MRAM. Power-intermittence resiliency is also enhanced by retaining the partial state information needed to maintain computational forward-progress, which is advantageous for battery-less IoT nodes. Simulation results indicate ∼ 5.4× higher energy-efficiency and 9× speedup over ReRAM-based acceleration, or roughly ∼ 9.7× higher energy-efficiency and 13.5× speedup over recent CMOS-only approaches, while maintaining inference accuracy comparable to baseline designs.

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Roohi A, Angizi S, Fan D, Demara RF. Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society. 2019. p. 8-13. 8697572. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2019.8697572

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience

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