Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency

Li Yang, Zhezhi He, Shaahin Angizi, Deliang Fan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the widely deployment of powerful deep neural network (DNN) into smart, but resource limited IoT devices, many prior works have been proposed to compress DNN in a hardware-aware manner to reduce the computing complexity, while maintaining accuracy, such as weight quantization, pruning, convolution decomposition, etc. However, in typical DNN compression methods, a smaller, but fixed, network structure is generated from a relative large background model for resource limited hardware accelerator deployment. However, such optimization lacks the ability to tune its structure on-the-fly to best fit for a dynamic computing hardware resource allocation and workloads. In this paper, we mainly review two of our prior works [1], [2] to address this issue, discussing how to construct a dynamic DNN structure through either uniform or non-uniform channel selection based sub-network sampling. The constructed dynamic DNN could tune its computing path to involve different number of channels, thus providing the ability to trade-off between speed, power and accuracy on-the-fly after model deployment. Correspondingly, an emerging Spin-Orbit Torque Magnetic Random-Access-Memory (SOT-MRAM) based Processing-In-Memory (PIM) accelerator will also be discussed for such dynamic neural network structure.

Original languageEnglish (US)
Title of host publicationProceedings - 33rd IEEE International System on Chip Conference, SOCC 2020
EditorsGang Qu, Jinjun Xiong, Danella Zhao, Venki Muthukumar, Md Farhadur Reza, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages117-122
Number of pages6
ISBN (Electronic)9781728187457
DOIs
StatePublished - Sep 8 2020
Externally publishedYes
Event33rd IEEE International System on Chip Conference, SOCC 2020 - Virtual, Las Vegas, United States
Duration: Sep 8 2020Sep 11 2020

Publication series

NameInternational System on Chip Conference
Volume2020-September
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference33rd IEEE International System on Chip Conference, SOCC 2020
Country/TerritoryUnited States
CityVirtual, Las Vegas
Period9/8/209/11/20

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Keywords

  • Dynamic neural network
  • Processing-in-Memory

Fingerprint

Dive into the research topics of 'Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency'. Together they form a unique fingerprint.

Cite this