RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security

Sepehr Tabrizchi, Nedasadat Taheri, Shaahin Angizi, Arman Roohi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The widespread adoption of vision sensors raises significant security and privacy concerns. In this paper, we present RACSen as a novel architecture that can increase the security and efficiency of conventional image sensors. RACSen leverages the intricate mathematical properties of the residue number system (RNS) with analog scrambling techniques to create a sophisticated dual-layered encryption mechanism. Incorporating RNS within analog-to-digital converters further strengthens security by mitigating replay attacks and preserving data transmission integrity and confidentiality. Our results demonstrate exceptional encryption, with a perfect pixel change rate of 99.90 and high intensity change of 45.77. This offers robust image data protection with minimal overhead of 11.11%.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2024 - Proceedings of the Great Lakes Symposium on VLSI 2024
PublisherAssociation for Computing Machinery
Pages551-555
Number of pages5
ISBN (Electronic)9798400706059
DOIs
StatePublished - Jun 12 2024
Event34th Great Lakes Symposium on VLSI 2024, GLSVLSI 2024 - Clearwater, United States
Duration: Jun 12 2024Jun 14 2024

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference34th Great Lakes Symposium on VLSI 2024, GLSVLSI 2024
Country/TerritoryUnited States
CityClearwater
Period6/12/246/14/24

All Science Journal Classification (ASJC) codes

  • General Engineering

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