Abstract
A random access memory (RAM) testable design for both testing and diagnosis was presented. The testable design used linear feedback shift registers and a comparator to assist the built-in self-test (BIST). The test required only random data, hence the test length needed to be carefully assessed. The test length required to detect RAM faults depended on which faults are targeted. Hardware overhead for the test was very low and decreased with the increase in the size of the array.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 102-107 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Electronics |
| Volume | E84-C |
| Issue number | 1 |
| State | Published - Jan 2001 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering