TY - JOUR
T1 - Random pattern testability of control and address circuitry of an embedded memory with feed-forward data-path connections
AU - Savir, Jacob
N1 - Funding Information:
⁄This work was supported by NJCST under the R&D Excellence Program for the Center for Embedded System-on-a-Chip Design.
Copyright:
Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.
PY - 1999
Y1 - 1999
N2 - Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs, but may also be suitable for use with other detection probability tools and simulation tools.
AB - Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs, but may also be suitable for use with other detection probability tools and simulation tools.
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U2 - 10.1023/A:1008345026085
DO - 10.1023/A:1008345026085
M3 - Article
AN - SCOPUS:0033351194
SN - 0923-8174
VL - 15
SP - 279
EP - 296
JO - Journal of Electronic Testing: Theory and Applications (JETTA)
JF - Journal of Electronic Testing: Theory and Applications (JETTA)
IS - 3
ER -