RANDOM PATTERN TESTABILITY OF DELAY FAULTS.

Jacob Savir; W. H. McAnney

RANDOM PATTERN TESTABILITY OF DELAY FAULTS.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic.

Original language	English (US)
Title of host publication	Digest of Papers - International Test Conference
Publisher	IEEE
Pages	263-273
Number of pages	11
ISBN (Print)	0818607262
State	Published - Dec 1 1986
Externally published	Yes

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

@inproceedings{22e7a882282048f497e506d667178b50,

title = "RANDOM PATTERN TESTABILITY OF DELAY FAULTS.",

abstract = "In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic.",

author = "Jacob Savir and McAnney, {W. H.}",

year = "1986",

month = dec,

day = "1",

language = "English (US)",

isbn = "0818607262",

pages = "263--273",

booktitle = "Digest of Papers - International Test Conference",

publisher = "IEEE",

}

TY - GEN

T1 - RANDOM PATTERN TESTABILITY OF DELAY FAULTS.

AU - Savir, Jacob

AU - McAnney, W. H.

PY - 1986/12/1

Y1 - 1986/12/1

N2 - In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic.

AB - In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic.

UR - http://www.scopus.com/inward/record.url?scp=0022880990&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022880990&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0022880990

SN - 0818607262

SP - 263

EP - 273

BT - Digest of Papers - International Test Conference

PB - IEEE

ER -

RANDOM PATTERN TESTABILITY OF DELAY FAULTS.

Abstract

All Science Journal Classification (ASJC) codes

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