In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic.
|Original language||English (US)|
|Title of host publication||Digest of Papers - International Test Conference|
|Number of pages||11|
|State||Published - Dec 1 1986|
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