RANDOM PATTERN TESTABILITY OF DELAY FAULTS.

Jacob Savir, W. H. McAnney

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherIEEE
Pages263-273
Number of pages11
ISBN (Print)0818607262
StatePublished - Dec 1 1986
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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