Random Pattern Testability of Delay Faults

Jacob Savir; William H. Mcanney

doi:10.1109/12.2166

Random Pattern Testability of Delay Faults

Jacob Savir, William H. Mcanney

Research output: Contribution to journal › Article › peer-review

22 Scopus citations

Abstract

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic. Formulas that relate the length of the test to the desired test quality are derived.

Original language	English (US)
Pages (from-to)	291-300
Number of pages	10
Journal	IEEE Transactions on Computers
Volume	37
Issue number	3
DOIs	https://doi.org/10.1109/12.2166
State	Published - Mar 1988
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

Keywords

Delay test pairs
delay testing
hazard factor
hazard-free tests
random testing
testability

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10.1109/12.2166

Cite this

@article{2c6e7b8dd60f4882b12c8ae756e17e79,

title = "Random Pattern Testability of Delay Faults",

abstract = "In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic. Formulas that relate the length of the test to the desired test quality are derived.",

keywords = "Delay test pairs, delay testing, hazard factor, hazard-free tests, random testing, testability",

author = "Jacob Savir and Mcanney, {William H.}",

year = "1988",

month = mar,

doi = "10.1109/12.2166",

language = "English (US)",

volume = "37",

pages = "291--300",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

number = "3",

}

TY - JOUR

T1 - Random Pattern Testability of Delay Faults

AU - Savir, Jacob

AU - Mcanney, William H.

PY - 1988/3

Y1 - 1988/3

N2 - In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic. Formulas that relate the length of the test to the desired test quality are derived.

AB - In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic. Formulas that relate the length of the test to the desired test quality are derived.

KW - Delay test pairs

KW - delay testing

KW - hazard factor

KW - hazard-free tests

KW - random testing

KW - testability

UR - http://www.scopus.com/inward/record.url?scp=0023961716&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023961716&partnerID=8YFLogxK

U2 - 10.1109/12.2166

DO - 10.1109/12.2166

M3 - Article

AN - SCOPUS:0023961716

SN - 0018-9340

VL - 37

SP - 291

EP - 300

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 3

ER -

Random Pattern Testability of Delay Faults

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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