Random Pattern Testability of Delay Faults

Jacob Savir, William H. Mcanney

Research output: Contribution to journalArticlepeer-review

20 Scopus citations

Abstract

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. In this paper, we analyze the capability of random patterns to detect slow paths in combinational logic. Formulas that relate the length of the test to the desired test quality are derived.

Original languageEnglish (US)
Pages (from-to)291-300
Number of pages10
JournalIEEE Transactions on Computers
Volume37
Issue number3
DOIs
StatePublished - Mar 1988
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Keywords

  • Delay test pairs
  • delay testing
  • hazard factor
  • hazard-free tests
  • random testing
  • testability

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