Random pattern testability of memory address logic

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An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm.

Original languageEnglish (US)
Pages (from-to)1310-1318
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
StatePublished - 1998

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


  • Detection probability
  • Exposure probability
  • Markov chain
  • Random patterns
  • Signal probability


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