Abstract
An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm.
Original language | English (US) |
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Pages (from-to) | 1310-1318 |
Number of pages | 9 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 17 |
Issue number | 12 |
DOIs | |
State | Published - 1998 |
All Science Journal Classification (ASJC) codes
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
Keywords
- Detection probability
- Exposure probability
- Markov chain
- Random patterns
- Signal probability