Random pattern testability of memory control logic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE VLSI Test Symposium
Editors Anon
PublisherIEEE
Pages399-407
Number of pages9
StatePublished - Jan 1 1997
EventProceedings of the 1997 15th VLSI Test Symposium - Monterey, CA, USA
Duration: Apr 27 1997May 1 1997

Other

OtherProceedings of the 1997 15th VLSI Test Symposium
CityMonterey, CA, USA
Period4/27/975/1/97

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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