Random pattern testability of memory control logic

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

Original languageEnglish (US)
Pages (from-to)305-312
Number of pages8
JournalIEEE Transactions on Computers
Volume47
Issue number3
DOIs
StatePublished - Dec 1 1998

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Keywords

  • Detection probability
  • Markov chain
  • Memory BIST
  • Memory postlogic
  • Memory prelogic
  • Signal probability

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