Random pattern testability of memory control logic

Jacob Savir

doi:10.1109/12.660166

Random pattern testability of memory control logic

Jacob Savir

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

Original language	English (US)
Pages (from-to)	305-312
Number of pages	8
Journal	IEEE Transactions on Computers
Volume	47
Issue number	3
DOIs	https://doi.org/10.1109/12.660166
State	Published - 1998

All Science Journal Classification (ASJC) codes

Software
Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

Keywords

Detection probability
Markov chain
Memory BIST
Memory postlogic
Memory prelogic
Signal probability

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10.1109/12.660166

Cite this

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title = "Random pattern testability of memory control logic",

abstract = "This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.",

keywords = "Detection probability, Markov chain, Memory BIST, Memory postlogic, Memory prelogic, Signal probability",

author = "Jacob Savir",

year = "1998",

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AU - Savir, Jacob

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AB - This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

KW - Detection probability

KW - Markov chain

KW - Memory BIST

KW - Memory postlogic

KW - Memory prelogic

KW - Signal probability

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JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

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ER -

Random pattern testability of memory control logic

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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