Abstract
This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.
| Original language | English (US) |
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| Pages | 399-407 |
| Number of pages | 9 |
| State | Published - 1997 |
| Event | Proceedings of the 1997 15th VLSI Test Symposium - Monterey, CA, USA Duration: Apr 27 1997 → May 1 1997 |
Other
| Other | Proceedings of the 1997 15th VLSI Test Symposium |
|---|---|
| City | Monterey, CA, USA |
| Period | 4/27/97 → 5/1/97 |
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering