Improving the quality of random pattern test requires the identification of testability bottlenecks, those faults in the logic which are random-pattern resistant. The cutting algorithm is an O(N**2) complexity method of generating testability bounds on N-gate combinational structures. A technique which allows the cutting algorithm to deal with structures containing embedded random-access memories is described. The random pattern testability of combinational structures driving address decoder inputs of a multiport memory is considered.