RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.

J. Savir, W. H. McAnney, S. R. Vecchio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Improving the quality of random pattern test requires the identification of testability bottlenecks, those faults in the logic which are random-pattern resistant. The cutting algorithm is an O(N**2) complexity method of generating testability bounds on N-gate combinational structures. A technique which allows the cutting algorithm to deal with structures containing embedded random-access memories is described. The random pattern testability of combinational structures driving address decoder inputs of a multiport memory is considered.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherIEEE
Pages106-114
Number of pages9
ISBN (Print)081860641X
StatePublished - Dec 1 1985
Externally publishedYes

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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