RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.

J. Savir; W. H. McAnney; S. R. Vecchio

RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.

J. Savir
, W. H. McAnney
, S. R. Vecchio

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Improving the quality of random pattern test requires the identification of testability bottlenecks, those faults in the logic which are random-pattern resistant. The cutting algorithm is an O(N**2) complexity method of generating testability bounds on N-gate combinational structures. A technique which allows the cutting algorithm to deal with structures containing embedded random-access memories is described. The random pattern testability of combinational structures driving address decoder inputs of a multiport memory is considered.

Original language	English (US)
Title of host publication	Digest of Papers - International Test Conference
Publisher	IEEE
Pages	106-114
Number of pages	9
ISBN (Print)	081860641X
State	Published - 1985
Externally published	Yes

Publication series

Name	Digest of Papers - International Test Conference
ISSN (Print)	0743-1686

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

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title = "RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.",

abstract = "Improving the quality of random pattern test requires the identification of testability bottlenecks, those faults in the logic which are random-pattern resistant. The cutting algorithm is an O(N**2) complexity method of generating testability bounds on N-gate combinational structures. A technique which allows the cutting algorithm to deal with structures containing embedded random-access memories is described. The random pattern testability of combinational structures driving address decoder inputs of a multiport memory is considered.",

author = "J. Savir and McAnney, \{W. H.\} and Vecchio, \{S. R.\}",

year = "1985",

language = "English (US)",

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publisher = "IEEE",

pages = "106--114",

booktitle = "Digest of Papers - International Test Conference",

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AU - McAnney, W. H.

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PY - 1985

Y1 - 1985

N2 - Improving the quality of random pattern test requires the identification of testability bottlenecks, those faults in the logic which are random-pattern resistant. The cutting algorithm is an O(N**2) complexity method of generating testability bounds on N-gate combinational structures. A technique which allows the cutting algorithm to deal with structures containing embedded random-access memories is described. The random pattern testability of combinational structures driving address decoder inputs of a multiport memory is considered.

AB - Improving the quality of random pattern test requires the identification of testability bottlenecks, those faults in the logic which are random-pattern resistant. The cutting algorithm is an O(N**2) complexity method of generating testability bounds on N-gate combinational structures. A technique which allows the cutting algorithm to deal with structures containing embedded random-access memories is described. The random pattern testability of combinational structures driving address decoder inputs of a multiport memory is considered.

UR - https://www.scopus.com/pages/publications/0022291214

UR - https://www.scopus.com/pages/publications/0022291214#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0022291214

SN - 081860641X

T3 - Digest of Papers - International Test Conference

SP - 106

EP - 114

BT - Digest of Papers - International Test Conference

PB - IEEE

ER -

RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.

Abstract

Publication series

All Science Journal Classification (ASJC) codes

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