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RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.
J. Savir
, W. H. McAnney
, S. R. Vecchio
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
3
Scopus citations
Overview
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Dive into the research topics of 'RANDOM PATTERN TESTING FOR ADDRESS-LINE FAULTS IN AN EMBEDDED MULTIPORT MEMORY.'. Together they form a unique fingerprint.
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Keyphrases
Testability
100%
Multi-port Memory
100%
Line Fault
100%
Cutting Algorithm
66%
Combinational
66%
Random Access Memory
33%
Pattern Test
33%
Address Decoder
33%
Engineering
Testability
100%
Line Fault
100%
Address Line
100%
Multiport Memory
100%
Random Access Memory
33%
Address Decoder
33%
Computer Science
Random Pattern
100%
Multiport Memory
100%
Random Access Memory
33%
Random Test Pattern
33%