Reduced Latch Count Shift Registers

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%.

Original languageEnglish (US)
Pages (from-to)183-185
Number of pages3
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume11
Issue number2
DOIs
StatePublished - 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Keywords

  • LSSD
  • STUMPS architecture
  • Scan register
  • Shift register latch
  • Shifting clocks

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