Abstract
This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 183-185 |
| Number of pages | 3 |
| Journal | Journal of Electronic Testing: Theory and Applications (JETTA) |
| Volume | 11 |
| Issue number | 2 |
| DOIs | |
| State | Published - 1997 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Keywords
- LSSD
- STUMPS architecture
- Scan register
- Shift register latch
- Shifting clocks