Reducing read latency of phase change memory via early read and Turbo Read

Prashant J. Nair, Chiachen Chou, Bipin Rajendran, Moinuddin K. Qureshi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Scopus citations

Abstract

Phase Change Memory (PCM) is an emerging memory technology that can enable scalable high-density main memory systems. Unfortunately, PCM has higher read latency than DRAM, resulting in lower system performance. This paper investigates architectural techniques to improve the read latency of PCM. We observe that there is a wide distribution in cell resistance in both the SET state and the RESET state, and that the read latency of PCM is designed conservatively to handle the worst case cell. If PCM sensing can be tuned to exploit the variability in cell resistance, then we can get reduced read latency. We propose two schemes to enable better-than-worst-case read latency for PCM systems. Our first proposal, Early Read, reads the data earlier than the specified time period. Our key observation that Early Read causes only unidirectional errors (SET being read as RESET) allows us to efficiently detect data errors using Berger codes. In the uncommon case that Early Read causes data error(s), we simply retry the read operation with original latency. Our evaluations show that Early Read can reduce the read latency by 25% while incurring a storage overhead of only 10 bits per 64 byte line. Our second proposal, Turbo Read, reduces the sensing time for read operations by pumping higher current, at the expense of accidentally switching the PCM cell with small probability during the read operation. We analyze Error Correction Codes (ECC) and Probabilistic Row Scrubbing (PRS) for maintaining data integrity under Turbo Read. We show that a combination of Early Read and Turbo Read can reduce the PCM read latency by 30%, improve the system performance by 21%, and reduce the Energy Delay Product (EDP) by 28%, while requiring minimal changes to the memory system.

Original languageEnglish (US)
Title of host publication2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages309-319
Number of pages11
ISBN (Electronic)9781479989300
DOIs
StatePublished - Mar 6 2015
Externally publishedYes
Event2015 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015 - Burlingame, United States
Duration: Feb 7 2015Feb 11 2015

Publication series

Name2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015

Other

Other2015 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015
Country/TerritoryUnited States
CityBurlingame
Period2/7/152/11/15

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Keywords

  • Berger Codes
  • ECC
  • Error Detecting Codes
  • Phase Change Memory
  • Read Disturbance
  • Read Latency
  • Reliability

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