Reduction of timed marked graphs and its applications to manufacturing systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Marked graphs are an important class of Petri nets for modeling asynchronous concurrent systems. Their reduction theory has been well established. To evaluate the cycle time and other performance measures, their places and/or transitions can be associated with deterministic timing information. Analytical formulas is well known based on all loops in the graph. It has been used to derive the cycle time of shop-floor production system, robotic assembly system, and flexible manufacturing system cell. It is observed that a marked graph model grows with the system size and resulting in a complexity problem to find all the loops inside the model. To challenge this problem, this paper proposes a reduction theory and algorithm for timed marked graphs. Thus the stepwise reduction of timed marked graphs can be performed efficiently. This method has been used to evaluate a flexible manufacturing system (FMS) cell.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Robotics and Automation
PublisherPubl by IEEE
Pages801-806
Number of pages6
Editionpt 1
ISBN (Print)0818653329
StatePublished - Jan 1 1994
EventProceedings of the 1994 IEEE International Conference on Robotics and Automation - San Diego, CA, USA
Duration: May 8 1994May 13 1994

Publication series

NameProceedings - IEEE International Conference on Robotics and Automation
Numberpt 1
ISSN (Print)1050-4729

Other

OtherProceedings of the 1994 IEEE International Conference on Robotics and Automation
CitySan Diego, CA, USA
Period5/8/945/13/94

All Science Journal Classification (ASJC) codes

  • Software
  • Control and Systems Engineering
  • Artificial Intelligence
  • Electrical and Electronic Engineering

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