TY - GEN
T1 - Resource-driven optimizations for transient-fault detecting superscalar microarchitectures
AU - Hu, Jie S.
AU - Link, G. M.
AU - John, Johnsy K.
AU - Wang, Shuai
AU - Ziavras, Sotirios G.
PY - 2005
Y1 - 2005
N2 - Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unaddressed. Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (FUS), 2) prioritizing primary instructions (PRI), and 3) early retiring of redundant instructions (ERT), that enable transient-fault detecting redundant execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement.
AB - Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unaddressed. Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (FUS), 2) prioritizing primary instructions (PRI), and 3) early retiring of redundant instructions (ERT), that enable transient-fault detecting redundant execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement.
UR - http://www.scopus.com/inward/record.url?scp=33646499628&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33646499628&partnerID=8YFLogxK
U2 - 10.1007/11572961_17
DO - 10.1007/11572961_17
M3 - Conference contribution
AN - SCOPUS:33646499628
SN - 3540296433
SN - 9783540296430
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 200
EP - 214
BT - Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings
PB - Springer Verlag
T2 - 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005
Y2 - 24 October 2005 through 26 October 2005
ER -