RPU: The Ring Processing Unit

Deepraj Soni, Negar Neda, Naifeng Zhang, Benedict Reynwar, Homer Gamil, Benjamin Heyman, Mohammed Nabeel, Ahmad Al Badawi, Yuriy Polyakov, Kellie Canida, Massoud Pedram, Michail Maniatakos, David Bruce Cousins, Franz Franchetti, Matthew French, Andrew Schmidt, Brandon Reagen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Ring-Learning-with-Errors (RLWE) has emerged as the foundation of many important techniques for improving security and privacy, including homomorphic encryption and post-quantum cryptography. While promising, these techniques have received limited use due to their extreme overheads of running on general-purpose machines. In this paper, we present a novel vector Instruction Set Architecture (ISA) and microarchitecture for accelerating the ring-based computations of RLWE. The ISA, named B512, is developed to meet the needs of ring processing workloads while balancing high-performance and general-purpose programming support. Having an ISA rather than fixed hardware facilitates continued software improvement post-fabrication and the ability to support the evolving workloads. We then propose the ring processing unit (RPU), a high-performance, modular implementation of B512. The RPU has native large word modular arithmetic support, capabilities for very wide parallel processing, and a large capacity highbandwidth scratchpad to meet the needs of ring processing. We address the challenges of programming the RPU using a newly developed SPIRAL backend. A configurable simulator is built to characterize design tradeoffs and quantify performance. The best performing design was implemented in RTL and used to validate simulator performance. In addition to our characterization, we show that a RPU using 20.5mm2 of GF12nm can provide a speedup of 1485× over a CPU running a 64k, 128-bit NTT, a core RLWE workload.

Original languageEnglish (US)
Title of host publicationProceedings - 2023 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages272-282
Number of pages11
ISBN (Electronic)9798350397390
DOIs
StatePublished - 2023
Externally publishedYes
Event2023 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023 - Raleigh, United States
Duration: Apr 23 2023Apr 25 2023

Publication series

NameProceedings - 2023 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023

Conference

Conference2023 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023
Country/TerritoryUnited States
CityRaleigh
Period4/23/234/25/23

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems
  • Software
  • Safety, Risk, Reliability and Quality
  • Modeling and Simulation

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