RTA processing of W-polycide dual-gate sub-micron structures for low-voltage CMOS technology

J. Bevk, M. Furtsch, G. E. Georgiou, S. J. Hillenius, D. Schielein, T. Schiml, P. J. Silverman, H. S. Luftman

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

Deep submicron CMOS technology for low-power, low-voltage applications requires the use of symmetric n+/p+ poly gate structures. This requirement introduces a number of processing challenges, involving fundamental issues of atomic diffusion over distances of 1angstrom to approx.30μm. Two of the critical issues are dopant cross-diffusion between P- and NMOS devices with connected gates, resulting in large threshold voltage shifts, and boron penetration through the gate oxide. We show that in devices with W-polycide dual-gate structure most of these problems can be alleviated by using rapid thermal annealing, RTA, in combination with a few additional, simple processing steps (e. g., low-temperature recrystallization of a-Si layer and selective nitrogen co-implants). The RTA step, in particular, ensures that the boron activation in the p+ poly-Si remains high and negates any effects of arsenic cross-diffusion. CMOS devices with properly processed gates have low gate stack profiles, small threshold voltage shifts (<30mV), and excellent device characteristics.

Original languageEnglish (US)
Pages (from-to)115-120
Number of pages6
JournalMaterials Research Society Symposium - Proceedings
Volume429
DOIs
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 MRS Spring Symposium - San Francisco, CA, USA
Duration: Apr 8 1996Apr 12 1996

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

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