Scalable multifolded hypercubes for versatile parallel computers

This paper introduces the family of scalable multifolded hypercube (SMH) architectures for parallel computers. Scalability and versatility at reasonable cost are the major characteristics of these architectures. SMHs perform comparable to generalized hypercubes for important classes of algorithms that use regular communication patterns. In addition, they often achieve better performance than the popular direct binary hypercubes because they can emulate efficiently a powerful family of multifolded direct binary hypercubes. Extensive comparison of cost with binary and generalized hypercubes is also included. The hardware cost of SMH's is shown to be even lower than that of fat trees. Therefore, SMH's are viable candidates for the construction of versatile parallel computers.