Scan latch design for delay test

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations

Abstract

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.

Original languageEnglish (US)
Pages (from-to)446-453
Number of pages8
JournalIEEE International Test Conference (TC)
StatePublished - Dec 1 1997
EventProceedings of the 1997 IEEE International Test Conference - Washington, DC, USA
Duration: Nov 3 1997Nov 5 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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