Abstract
This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 446-453 |
| Number of pages | 8 |
| Journal | IEEE International Test Conference (TC) |
| State | Published - 1997 |
| Event | Proceedings of the 1997 IEEE International Test Conference - Washington, DC, USA Duration: Nov 3 1997 → Nov 5 1997 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics