Scan latch design for test applications

Amit M. Sheth, Jacob Savir

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Original languageEnglish (US)
Pages (from-to)213-216
Number of pages4
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Issue number2
StatePublished - Apr 2004

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


  • Hardware overhead
  • LSSD
  • Scan design
  • Shift register latch


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