Scan latch design for test applications

Amit M. Sheth; Jacob Savir

doi:10.1023/B:JETT.0000023683.62501.ed

Scan latch design for test applications

Amit M. Sheth, Jacob Savir

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Original language	English (US)
Pages (from-to)	213-216
Number of pages	4
Journal	Journal of Electronic Testing: Theory and Applications (JETTA)
Volume	20
Issue number	2
DOIs	https://doi.org/10.1023/B:JETT.0000023683.62501.ed
State	Published - Apr 2004

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Keywords

Hardware overhead
LSSD
Scan design
Shift register latch

Access to Document

10.1023/B:JETT.0000023683.62501.ed

Cite this

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title = "Scan latch design for test applications",

abstract = "This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.",

keywords = "Hardware overhead, LSSD, Scan design, Shift register latch",

author = "Sheth, {Amit M.} and Jacob Savir",

year = "2004",

month = apr,

doi = "10.1023/B:JETT.0000023683.62501.ed",

language = "English (US)",

volume = "20",

pages = "213--216",

journal = "Journal of Electronic Testing: Theory and Applications (JETTA)",

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T1 - Scan latch design for test applications

AU - Sheth, Amit M.

AU - Savir, Jacob

PY - 2004/4

Y1 - 2004/4

N2 - This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

AB - This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

KW - Hardware overhead

KW - LSSD

KW - Scan design

KW - Shift register latch

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U2 - 10.1023/B:JETT.0000023683.62501.ed

DO - 10.1023/B:JETT.0000023683.62501.ed

M3 - Article

AN - SCOPUS:3543107787

SN - 0923-8174

VL - 20

SP - 213

EP - 216

JO - Journal of Electronic Testing: Theory and Applications (JETTA)

JF - Journal of Electronic Testing: Theory and Applications (JETTA)

IS - 2

ER -

Scan latch design for test applications

Abstract

All Science Journal Classification (ASJC) codes

Keywords

Access to Document

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