SELF: A High Performance and Bandwidth Efficient Approach to Exploiting Die-Stacked DRAM as Part of Memory

Keyphrases

• Bandwidth Efficient 100%
• Bandwidth Utilization 20%
• Cache Design 20%
• Caching 20%
• EDRAM 60%
• Energy Consumption 20%
• High Bandwidth 100%
• High Performance 100%
• Hit Ratio 60%
• Instruction per Cycle 20%
• Large Amount of Data 20%
• Line-based 40%
• Low Latency 20%
• Main Memory 20%
• Memory Access 20%
• Memory Bandwidth 20%
• Memory Design 60%
• Memory Systems 40%
• Memory Wall 20%
• Off-chip Bandwidth 40%
• On chip 60%
• On-chip Memory 100%
• Page Fault 20%
• Page-based 80%
• Performance Degradation 20%
• Promising Technology 20%
• Stacked DRAM 100%
• Swap Lines 20%
• System Performance 20%
• Temporal Locality 20%

Computer Science

• Bandwidth Utilization 66%
• Energy Consumption 33%
• Instructions per Cycle 33%
• Main Memory 33%
• Memory Access 33%
• Memory Bandwidth 33%
• Memory Design 100%
• Memory System 66%
• Page Fault 33%
• Performance Degradation 33%
• Systems Performance 33%
• Temporal Locality 33%
• Total Capacity 33%