TY - GEN
T1 - SenTer
T2 - 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
AU - Tabrizchi, Sepehr
AU - Gaire, Rebati
AU - Angizi, Shaahin
AU - Roohi, Arman
N1 - Publisher Copyright:
© 2023 ACM.
PY - 2023/6/5
Y1 - 2023/6/5
N2 - Recently, Intelligent IoT (IIoT), including various sensors, has gained significant attention due to its capability of sensing, deciding, and acting by leveraging artificial neural networks (ANN). Nevertheless, to achieve acceptable accuracy and high performance in visual systems, a power-delay-efficient architecture is required. In this paper, we propose an ultra-low-power processing in-sensor architecture, namely SenTer, realizing low-precision ternary multi-layer perceptron networks, which can operate in detection and classification modes. Moreover, SenTer supports two activation functions based on user needs and the desired accuracy-energy trade-off. SenTer is capable of performing all the required computations for the MLP's first layer in the analog domain and then submitting its results to a co-processor. Therefore, SenTer significantly reduces the overhead of analog buffers, data conversion, and transmission power consumption by using only one ADC. Additionally, our simulation results demonstrate acceptable accuracy on various datasets compared to the full precision models.
AB - Recently, Intelligent IoT (IIoT), including various sensors, has gained significant attention due to its capability of sensing, deciding, and acting by leveraging artificial neural networks (ANN). Nevertheless, to achieve acceptable accuracy and high performance in visual systems, a power-delay-efficient architecture is required. In this paper, we propose an ultra-low-power processing in-sensor architecture, namely SenTer, realizing low-precision ternary multi-layer perceptron networks, which can operate in detection and classification modes. Moreover, SenTer supports two activation functions based on user needs and the desired accuracy-energy trade-off. SenTer is capable of performing all the required computations for the MLP's first layer in the analog domain and then submitting its results to a co-processor. Therefore, SenTer significantly reduces the overhead of analog buffers, data conversion, and transmission power consumption by using only one ADC. Additionally, our simulation results demonstrate acceptable accuracy on various datasets compared to the full precision models.
KW - low-power cmos imager
KW - multi-layer perceptron
KW - processing in-sensor
UR - http://www.scopus.com/inward/record.url?scp=85163180170&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85163180170&partnerID=8YFLogxK
U2 - 10.1145/3583781.3590225
DO - 10.1145/3583781.3590225
M3 - Conference contribution
AN - SCOPUS:85163180170
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 497
EP - 502
BT - GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
PB - Association for Computing Machinery
Y2 - 5 June 2023 through 7 June 2023
ER -