Abstract
Sequential fabrication of CMOS devices one above the other on isolated crystalline templates could enable the manufacture of 3D Integrated circuits with more than a million inter-layer wires per square millimeter. Low thermal budget techniques such as pulsed laser annealing and chemical vapor deposition techniques are key to such a process.
Original language | English (US) |
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Pages | 101-107 |
Number of pages | 7 |
State | Published - 2006 |
Externally published | Yes |
Event | 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 - Fremont, CA, United States Duration: Sep 26 2006 → Sep 28 2006 |
Other
Other | 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 |
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Country/Territory | United States |
City | Fremont, CA |
Period | 9/26/06 → 9/28/06 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering