Sequential 3D IC fabrication-Challenges and prospects

Bipin Rajendran

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

Sequential fabrication of CMOS devices one above the other on isolated crystalline templates could enable the manufacture of 3D Integrated circuits with more than a million inter-layer wires per square millimeter. Low thermal budget techniques such as pulsed laser annealing and chemical vapor deposition techniques are key to such a process.

Original languageEnglish (US)
Pages101-107
Number of pages7
StatePublished - Dec 1 2006
Externally publishedYes
Event23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 - Fremont, CA, United States
Duration: Sep 26 2006Sep 28 2006

Other

Other23rd International VLSI Multilevel Interconnection Conference, VMIC 2006
Country/TerritoryUnited States
CityFremont, CA
Period9/26/069/28/06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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