Single-clock, single-latch, scan design

Amit M. Sheth; Jacob Savir

doi:10.1109/TIM.2003.818550

Single-clock, single-latch, scan design

Amit M. Sheth, Jacob Savir

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This correspondence describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Original language	English (US)
Pages (from-to)	1455-1457
Number of pages	3
Journal	IEEE Transactions on Instrumentation and Measurement
Volume	52
Issue number	5
DOIs	https://doi.org/10.1109/TIM.2003.818550
State	Published - Oct 2003

All Science Journal Classification (ASJC) codes

Instrumentation
Electrical and Electronic Engineering

Keywords

Hardware overhead
Level sensitive scan design (LSSD)
Scan design
Shift register latch

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10.1109/TIM.2003.818550

Cite this

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title = "Single-clock, single-latch, scan design",

abstract = "This correspondence describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.",

keywords = "Hardware overhead, Level sensitive scan design (LSSD), Scan design, Shift register latch",

author = "Sheth, {Amit M.} and Jacob Savir",

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KW - Level sensitive scan design (LSSD)

KW - Scan design

KW - Shift register latch

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Single-clock, single-latch, scan design

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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