Single-clock, single-latch, scan design

Amit M. Sheth, Jacob Savir

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


This correspondence describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Original languageEnglish (US)
Pages (from-to)1455-1457
Number of pages3
JournalIEEE Transactions on Instrumentation and Measurement
Issue number5
StatePublished - Oct 2003

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Electrical and Electronic Engineering


  • Hardware overhead
  • Level sensitive scan design (LSSD)
  • Scan design
  • Shift register latch


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