Single-clock, single-latch, scan design

Amit M. Sheth, Jacob Savir

Research output: Contribution to conferencePaperpeer-review


This paper describes a new scan design that uses the same clock for both scan and functional mode. A test mode signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Original languageEnglish (US)
Number of pages3
StatePublished - 2002
Event19th IEEE Instrumentation and Measurement Technology Conference - Anchorage, AK, United States
Duration: May 21 2002May 23 2002


Other19th IEEE Instrumentation and Measurement Technology Conference
Country/TerritoryUnited States
CityAnchorage, AK

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


  • Hardware overhead
  • LSSD
  • Scan design
  • Shift register latch


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