Single-clock, single-latch, scan design

Amit M. Sheth; Jacob Savir

Single-clock, single-latch, scan design

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes a new scan design that uses the same clock for both scan and functional mode. A test mode signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Original language	English (US)
Pages	613-615
Number of pages	3
State	Published - 2002
Event	19th IEEE Instrumentation and Measurement Technology Conference - Anchorage, AK, United States Duration: May 21 2002 → May 23 2002

Other

Other	19th IEEE Instrumentation and Measurement Technology Conference
Country/Territory	United States
City	Anchorage, AK
Period	5/21/02 → 5/23/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Keywords

Hardware overhead
LSSD
Scan design
Shift register latch

Cite this

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title = "Single-clock, single-latch, scan design",

abstract = "This paper describes a new scan design that uses the same clock for both scan and functional mode. A test mode signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.",

keywords = "Hardware overhead, LSSD, Scan design, Shift register latch",

author = "Sheth, \{Amit M.\} and Jacob Savir",

year = "2002",

language = "English (US)",

pages = "613--615",

note = "19th IEEE Instrumentation and Measurement Technology Conference ; Conference date: 21-05-2002 Through 23-05-2002",

}

TY - CONF

T1 - Single-clock, single-latch, scan design

AU - Sheth, Amit M.

AU - Savir, Jacob

PY - 2002

Y1 - 2002

N2 - This paper describes a new scan design that uses the same clock for both scan and functional mode. A test mode signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

AB - This paper describes a new scan design that uses the same clock for both scan and functional mode. A test mode signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

KW - Hardware overhead

KW - LSSD

KW - Scan design

KW - Shift register latch

UR - https://www.scopus.com/pages/publications/0036047837

UR - https://www.scopus.com/inward/citedby.url?scp=0036047837&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0036047837

SP - 613

EP - 615

T2 - 19th IEEE Instrumentation and Measurement Technology Conference

Y2 - 21 May 2002 through 23 May 2002

ER -

Single-clock, single-latch, scan design

Abstract

Other

All Science Journal Classification (ASJC) codes

Keywords

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