Abstract
This correspondence describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1455-1457 |
| Number of pages | 3 |
| Journal | IEEE Transactions on Instrumentation and Measurement |
| Volume | 52 |
| Issue number | 5 |
| DOIs | |
| State | Published - Oct 2003 |
All Science Journal Classification (ASJC) codes
- Instrumentation
- Electrical and Electronic Engineering
Keywords
- Hardware overhead
- Level sensitive scan design (LSSD)
- Scan design
- Shift register latch