@inproceedings{fa5af3e42ad84d95b158916bc9017908,

title = "Skewed-Load Transition Test: Part I, Calculus",

abstract = "A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs in principle when testing the combinational logic residing between scan chains. In the skewedload test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e. one bit-shift) pattern in the scan chain. This paper describes a calculus that allows one to compute the complete set of skewed-load transition test vectors. The calculus is capable of simultaneously computing both the first and second vector of the delay test pair. Probabilistic analysis of random pattern skewedload-based transition test is also discussed in this paper. We show how to extend both the Parker-McCluskey algorithm and the cutting algorithm to compute detection probability of transition faults.",

keywords = "Calculus, Circuit faults, Circuit testing, Clocks, Delay effects, Electrical fault detection, Fault detection, Logic circuits, Logic testing, Propagation delay",

author = "J. Savir",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; International Test Conference, ITC 1992 ; Conference date: 20-09-1992 Through 24-09-1992",

year = "1992",

doi = "10.1109/TEST.1992.527892",

language = "English (US)",

series = "Proceedings - International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "705--713",

booktitle = "Proceedings International Test Conference, ITC 1992",

address = "United States",

}