Skewed-Load Transition Test: Part I, Calculus

Research output: Chapter in Book/Report/Conference proceedingConference contribution

119 Scopus citations

Abstract

A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs in principle when testing the combinational logic residing between scan chains. In the skewedload test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e. one bit-shift) pattern in the scan chain. This paper describes a calculus that allows one to compute the complete set of skewed-load transition test vectors. The calculus is capable of simultaneously computing both the first and second vector of the delay test pair. Probabilistic analysis of random pattern skewedload-based transition test is also discussed in this paper. We show how to extend both the Parker-McCluskey algorithm and the cutting algorithm to compute detection probability of transition faults.

Original languageEnglish (US)
Title of host publicationProceedings International Test Conference, ITC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages705-713
Number of pages9
ISBN (Electronic)9780780307605
DOIs
StatePublished - Jan 1 1992
Externally publishedYes
EventInternational Test Conference, ITC 1992 - Baltimore, United States
Duration: Sep 20 1992Sep 24 1992

Publication series

NameProceedings - International Test Conference
Volume1992-January
ISSN (Print)1089-3539

Other

OtherInternational Test Conference, ITC 1992
CountryUnited States
CityBaltimore
Period9/20/929/24/92

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Keywords

  • Calculus
  • Circuit faults
  • Circuit testing
  • Clocks
  • Delay effects
  • Electrical fault detection
  • Fault detection
  • Logic circuits
  • Logic testing
  • Propagation delay

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