@inproceedings{d90282c7dc194181bd02f558a00e0c75,
title = "Skewed-Load Transition Test: Part II, Coverage",
abstract = "A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.",
keywords = "Capacitance, Circuit faults, Circuit testing, Clocks, Combinational circuits, Jacobian matrices, Latches, Logic circuits, Logic testing, Propagation delay",
author = "S. Patil and J. Savir",
note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; International Test Conference, ITC 1992 ; Conference date: 20-09-1992 Through 24-09-1992",
year = "1992",
doi = "10.1109/TEST.1992.527893",
language = "English (US)",
series = "Proceedings - International Test Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "714--722",
booktitle = "Proceedings International Test Conference, ITC 1992",
address = "United States",
}