Skewed-Load Transition Test: Part II, Coverage

S. Patil, J. Savir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

59 Scopus citations

Abstract

A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.

Original languageEnglish (US)
Title of host publicationProceedings International Test Conference, ITC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages714-722
Number of pages9
ISBN (Electronic)9780780307605
DOIs
StatePublished - Jan 1 1992
Externally publishedYes
EventInternational Test Conference, ITC 1992 - Baltimore, United States
Duration: Sep 20 1992Sep 24 1992

Publication series

NameProceedings - International Test Conference
Volume1992-January
ISSN (Print)1089-3539

Other

OtherInternational Test Conference, ITC 1992
CountryUnited States
CityBaltimore
Period9/20/929/24/92

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Keywords

  • Capacitance
  • Circuit faults
  • Circuit testing
  • Clocks
  • Combinational circuits
  • Jacobian matrices
  • Latches
  • Logic circuits
  • Logic testing
  • Propagation delay

Fingerprint Dive into the research topics of 'Skewed-Load Transition Test: Part II, Coverage'. Together they form a unique fingerprint.

Cite this