TY - JOUR
T1 - Successive packing based interleaver design for turbo codes
AU - Zhang, X. M.
AU - Shi, Y. Q.
AU - Chen, H.
AU - Haimovich, A. M.
AU - Vetro, A.
AU - Sun, H.
PY - 2002
Y1 - 2002
N2 - Interleaver is the key component in both turbo encoder and decoder. It has been shown that the good turbo codes performance can be obtained by using pseudo-random interleaver. However, it is difficult to analyze the corresponding pseudo-random algorithms such that the performance can be guaranteed, and furthermore they are computational expensive. In this paper, we focus on deterministic turbo codes interleaver design. A novel successive packing (SP) based turbo codes interleaver design method is proposed. In this method, the interleaver is generated based on packing of the basis interleaver iteratively. We have shown that SP based interleavers possess the following desirable features: prunability, adaptability to various criteria, and pseudo-random distribution. Simulation results demonstrate the superior performance of SP over other deterministic interleaver design techniques.
AB - Interleaver is the key component in both turbo encoder and decoder. It has been shown that the good turbo codes performance can be obtained by using pseudo-random interleaver. However, it is difficult to analyze the corresponding pseudo-random algorithms such that the performance can be guaranteed, and furthermore they are computational expensive. In this paper, we focus on deterministic turbo codes interleaver design. A novel successive packing (SP) based turbo codes interleaver design method is proposed. In this method, the interleaver is generated based on packing of the basis interleaver iteratively. We have shown that SP based interleavers possess the following desirable features: prunability, adaptability to various criteria, and pseudo-random distribution. Simulation results demonstrate the superior performance of SP over other deterministic interleaver design techniques.
UR - http://www.scopus.com/inward/record.url?scp=0036286332&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036286332&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2002.1009766
DO - 10.1109/ISCAS.2002.1009766
M3 - Article
AN - SCOPUS:0036286332
SN - 0271-4310
VL - 1
SP - 17-x20
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
ER -