SYMMETRIC SUBMICRON CMOS TECHNOLOGY.

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi//2 source/drains with sheet resistivities of 1. 5-2 OMEGA /square, n plus and p plus polysilicon/TaSi//2 gate structures, threshold voltages of 0. 4 V and 1. 5- mu m separation between active to tub-edge regions. Diode characteristics of the CoSi//2/n plus and CoSi//2/p plus are determined to be as good as nonsilicided silicon junctions. Maintaining the proper doping for the connected n plus and p plus polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3. 5 V are observed for devices with 0. 5- mu m channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1. 0 V due to the low threshold voltage of the transistors.