SYMMETRIC SUBMICRON CMOS TECHNOLOGY.

S. J. Hillenius, R. Liu, G. E. Georgiou, R. L. Field, D. S. Williams, A. Kornblit, D. M. Boulin, R. L. Johnston, W. T. Lynch

Research output: Contribution to journalConference articlepeer-review

52 Scopus citations

Abstract

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi//2 source/drains with sheet resistivities of 1. 5-2 OMEGA /square, n plus and p plus polysilicon/TaSi//2 gate structures, threshold voltages of 0. 4 V and 1. 5- mu m separation between active to tub-edge regions. Diode characteristics of the CoSi//2/n plus and CoSi//2/p plus are determined to be as good as nonsilicided silicon junctions. Maintaining the proper doping for the connected n plus and p plus polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3. 5 V are observed for devices with 0. 5- mu m channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1. 0 V due to the low threshold voltage of the transistors.

Original languageEnglish (US)
Pages (from-to)252-255
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - Dec 1 1986
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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