Abstract
In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design. In this correspondence we show a method of syndrome-testing circuits which are not “syndrome-testable.” The idea is to perform multiple constrained syndrome-tests on various portions of the circuits in such a way that an overall full syndrome-test coverage will be achieved. Thus, with this method the extra pin-penalty associated with the-testable design is traded off with the extra running time of the syndrome-test procedure.
Original language | English (US) |
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Pages (from-to) | 606-608 |
Number of pages | 3 |
Journal | IEEE Transactions on Computers |
Volume | C-30 |
Issue number | 8 |
DOIs | |
State | Published - Aug 1981 |
Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
Keywords
- Inversion parity
- reconvergent fan-out
- unate function