Syndrome-Testing of “Syndrome-Untestable” Combinational Circuits

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In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design. In this correspondence we show a method of syndrome-testing circuits which are not “syndrome-testable.” The idea is to perform multiple constrained syndrome-tests on various portions of the circuits in such a way that an overall full syndrome-test coverage will be achieved. Thus, with this method the extra pin-penalty associated with the-testable design is traded off with the extra running time of the syndrome-test procedure.

Original languageEnglish (US)
Pages (from-to)606-608
Number of pages3
JournalIEEE Transactions on Computers
Issue number8
StatePublished - Aug 1981
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


  • Inversion parity
  • reconvergent fan-out
  • unate function


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