Syndrome-Testing of “Syndrome-Untestable” Combinational Circuits

In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design. In this correspondence we show a method of syndrome-testing circuits which are not “syndrome-testable.” The idea is to perform multiple constrained syndrome-tests on various portions of the circuits in such a way that an overall full syndrome-test coverage will be achieved. Thus, with this method the extra pin-penalty associated with the-testable design is traded off with the extra running time of the syndrome-test procedure.