System-level energy modeling for heterogeneous reconfigurable chip multiprocessors

Keyphrases

• System Level 100%
• Design Methodology 100%
• Multiprocessor 100%
• Reconfigurable 100%
• Level Energies 100%
• Programmable chip 100%
• Chip multiprocessor 100%
• Energy Modeling 100%
• Energy Consumption 50%
• System Design 50%
• Field Programmable Gate Arrays 50%
• Reconfiguration 50%
• Application System 50%
• Programmability 50%
• Hardware Components 50%
• Reconfigurable Architectures 50%
• Design Cycle 50%
• Large Sparse Matrices 50%
• Microarray Technology 50%
• Energy Estimates 50%
• Energy-performance Tradeoff 50%
• Xilinx FPGA 50%
• Recent Trends 50%
• Real Need 50%
• Parallel LU Factorization 50%
• Continuous Improvement 50%
• Physical Level 50%
• Component Library 50%
• Energy Estimation Model 50%
• Level Measurement 50%

Engineering

• Energy Engineering 100%
• Level Energy 100%
• Energy Modeling 100%
• Field Programmable Gate Arrays 66%
• Early Stage 33%
• Application Specific Integrated Circuit 33%
• Design System 33%
• Powerful Tool 33%
• Programmability 33%
• Field Programmable Gate Array Technology 33%
• Energy Performance 33%
• Level Measurement 33%
• Reconfigurability 33%
• Hardware Component 33%
• Design Cycle 33%

Computer Science

• multi-processor 100%
• Chip Multiprocessor 100%
• Energy Consumption 50%
• Field Programmable Gate Arrays 50%
• Application System 50%
• Programmability 50%
• Application Specific Integrated Circuit 50%
• reconfigurable architecture 50%
• Energy Performance 50%
• Hardware Component 50%