Temperature Effects on Characteristics of High-k Gate Dielectrics With Metal Gates

In this paper, the temperature dependence of time-dependent dielectric breakdown (BD) and stress-induced leakage current (SILC) of high-k and interfacial layers (ILs) are studied separately and in a gate stack with metal gates as the BD mechanisms of these layers are different at higher temperatures than at room temperature. As observed from the low voltage SILC, the IL initiates the gate stack BD process at elevated temperature, which is followed by the high-k layer. Activation energy extracted from Weibulll distribution of time-to-BD (tbd) data from high-k layer further suggests that the gate stack BD occurs when high-k layer ultimately breaks down.