Test generators need to be modified to handle CMOS designs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CMOS designs have some unique properties that prevent existing test generators from computing a test vector for a fault when one might exist. The problem lies in the premises laid out on what it takes to detect a stuck-at fault. The basic premise that states that it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and then propagate the error to an observable point, is not a necessary and sufficient detection condition. This is due to the existence of unknown states throughout the logic. This paper shows an example to illustrate the problem; describes what it takes in order to remedy it; proposes possible enhancements to existing test generation algorithms, and outlines the risks faced in the event that no correcting steps are taken.

Original languageEnglish (US)
Title of host publicationIMTC 1997 - IEEE Instrumentation and Measurement Technology Conference
Subtitle of host publicationSensing, Processing, Networking, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1436-1441
Number of pages6
ISBN (Electronic)0780337476
DOIs
StatePublished - 1997
Event14th Annual IEEE Instrumentation and Measurement Technology Conference, IMTC 1997 - Ottawa, Canada
Duration: May 19 1997May 21 1997

Publication series

NameConference Record - IEEE Instrumentation and Measurement Technology Conference
Volume2
ISSN (Print)1091-5281

Other

Other14th Annual IEEE Instrumentation and Measurement Technology Conference, IMTC 1997
CountryCanada
CityOttawa
Period5/19/975/21/97

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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