CMOS designs have some unique properties that prevent existing test generators from computing a test vector for a fault when one might exist. The problem lies in the premises laid out on what it takes to detect a stuck-at fault. The basic premise that states that it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and then propagate the error to an observable point, is not a necessary and sufficient detection condition. This is due to the existence of unknown states throughout the logic. This paper shows an example to illustrate the problem; describes what it takes in order to remedy it; proposes possible enhancements to existing test generation algorithms, and outlines the risks faced in the event that no correcting steps are taken.
|Title of host publication
|IMTC 1997 - IEEE Instrumentation and Measurement Technology Conference
|Subtitle of host publication
|Sensing, Processing, Networking, Proceedings
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 1997
|14th Annual IEEE Instrumentation and Measurement Technology Conference, IMTC 1997 - Ottawa, Canada
Duration: May 19 1997 → May 21 1997
|Conference Record - IEEE Instrumentation and Measurement Technology Conference
|14th Annual IEEE Instrumentation and Measurement Technology Conference, IMTC 1997
|5/19/97 → 5/21/97
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering